1. Field of the Invention
The present invention relates to a multi-chip package, which is a semiconductor memory device including a plurality of semiconductor memories mounted thereon.
2. Description of the Related Art
Recently, multi-chip packages (hereinafter, referred to as “MCP”) including a plurality of semiconductor memories accommodated in one package are used in order to meet the recent requirement for more and more compact electronic devices (see, for example, U.S. Pat. No. 7,149,135). Such a plurality of semiconductor memories accommodated in one package may be of an identical type or of different types. In the latter case, the semiconductor memories are different in the line arrangement and circuit structure due to the difference in the operating environment such as the signals to be input thereto or the like. Such a difference in the line arrangement and circuit structure causes a delay of the input signals or the like, which undesirably lowers the performance of the package.
Japanese Laid-Open Patent Publications Nos. H11-102969, H11-31747, and H06-274241 describe technologies regarding semiconductor circuits, which are proposed to lower the delay in clock signals generated by the difference in load capacitance or the like, although not the technologies regarding MCPs.